Nanoscale Systems are currently being fabricated using many techniques adopted from the semiconductor and MEMS fields. These fabrication techniques create three dimensional structures by layering materials and patterning each layer (photolithography). Although such a process can create devices in parallel and thus produce large numbers of identical devices it is limited in its vertical scale capability. The aspect ratio (AR) of most planar processes is limited to a factor of a few units in the vertical dimension over the lateral dimension (AR of 3:1, for example). As the lateral dimension shrinks, so does the vertical and is confined to no more than an aspect ratio of 5:1 or so.
Reactive Ion Etching (RIE) has been pushed to achieve large aspect ratio via milling in nanoscale systems but it is limited to certain materials and the vertical walls cannot be made perpendicular. Subsequent process steps have to conform to the shape of the RIE formed process.
The materials that lend themselves to creating these structures are also limited to a few compounds and elements (silicon and its compounds, aluminum, titanium, copper, etc). Some of these compounds or elements are also incompatible with each other and have to be processed in special ways. For example, copper will diffuse in silicon and silicon dielectrics so it has to be completely encapsulated in a different material before it can be used in electrical circuits. This limits the scalability of copper in photolithographic processes.
In the area of structure modification, a very valuable application is circuit edit. Electronic semiconductor circuits have been modified in functionality and logic by using particle beam processes. However, these processes can only generate materials that are far inferior from the manufactured material (such as copper and dielectrics). See, generally, U.S. Pat. Nos. 7,297,946 and 5,364,497.